1. Field of the Invention
This application relates generally to integration circuit fabrication. More particularly, this application relates to the deposition of liners for through-silicon vias used in the 3-D integration of integrated circuits.
2. Description of the Related Art
Integrated circuits (ICs) typically include many devices and circuit features formed on a single semiconductor wafer. Current trends in IC technology are toward faster and more powerful circuits. However, as more complex ICs such as microprocessors having high operating frequency ranges are manufactured, various speed related problems are becoming increasingly challenging. This is especially true when ICs having different functions are used to create electronic systems, for example, computing systems including processor and memory ICs, where different ICs are electrically connected by a global interconnect network. As the global interconnects become longer and more numerous in the electronic system, RC delay and power consumption as well as low system performance are becoming limiting factors.
One proposed solution to these problems is three dimensional (3-D) integration or packaging technology, where 3-D integration refers to the vertical stacking of multiple dies or wafers including ICs within a package. In 3-D integration technology, multiple wafers are electrically connected using vertical connectors or 3-D conductive structures which can have depths or widths as large as one hundred micrometers or greater. Holes or vias (known as “through-silicon vias”) extending through one or more wafers can be filled with conductive material such as copper and can be aligned when the wafers are stacked to provide electrical communication among the ICs in the stacked wafers. Such 3-D integration can result in size and weight reduction of the IC package, reduction in power consumption, and an increase in performance and reliability.
A conventional method of forming an IC device using a 3-D integration technique will now be described. First, a wafer including substrate-level IC elements (e.g., transistors, capacitors, resistors, etc.) is provided. The front surface of the wafer is then coated with an insulating layer, such as a SiO2 film. One or more vias are then formed by etching, drilling (e.g., laser drilling) or a like process. For 3-D integrated devices, vias can be large, with the depths ranging from twenty microns to several hundred microns. The vias are typically in the fifty micron range. For some rounded vias, the diameters can range from one micron to over one hundred microns. After via formation, a dielectric film liner is coated on the wafer surface and also inside the vias for the purpose of insulating the wafer material from subsequently deposited conductive material. The dielectric film is then lined with a barrier layer such as a Ta/TaN layer and a seed layer. The via is then filled with conductive material using an electrochemical deposition or electroplating process to form one or more conductive plugs, followed by an optional chemical mechanical polishing (CMP) process or electrochemical mechanical polishing (EMCP) process to remove any unwanted conductive material from the surface of the wafer. A metallization layer is then formed and patterned to interconnect the substrate-level IC elements to the conductive plug. To expose the conductive plug embedded in the wafer, the wafer is thinned down to reveal the conductive plug from its back surface. The wafer may then be sliced into individual dies that are aligned and capable of being stacked on top of a base wafer. Eventually more levels of dies can be stacked on top of each other.
The development of 3-D integration continues and there is a continuing need for improved methods and systems for 3-D integration.